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oki semiconducto r pedl87v3116-02 issue date: sep. 21, 2004 ML87V3116 preliminary display controller with built-in display memory and jpeg 1/47 general description the ML87V3116 is a multi-function image processor lsi for small imaging devices. imaging functions, such as image input, temporary storag e, processing and display output, are integrated into a single chip. the ML87V3116 has functions includuing camera or video input image capture, display control in lcd or tv format, compression and decompression of s till pictures and moving pictures (motion-jpeg) using a jpeg engine, and image copying with the size reduction and the rotation. dram is embedded inside the chip to improve the performance of memory access and realize simultaneous operations of multiple functions. furthermore, by adding external memory, large-sized images can be processed and the moving pictures recording time can be extended. main features ? camera imaging : maximum 4 million pixels, 30 frames/sec at vga resolution (350,000 pixels) ? image compression/decompression : base line jpeg and motion-jpeg ? display controller : color tft-lcd up to vga, or tv format ? rectangle copy : magnification and reduction x1/2 to 1/32, rotation 0/90/180/270 ? built-in memory. : 8-mbit sdram ? external memory (optional) : sdram, 16/64/128/256/512 mbits, x16 types, 0 to 3 memory ? video input : ycbcr (4:2:2) 16-bit format x 1, or itu-r bt.656 (8-bit) format x 2 ? display output : 18/24 bits, rgb/ycbcr, 65536 colors ? operating frequency : maximum 28 mhz (internal 56 mhz) ? host interface : 8/16-bit bus (compatible with various microcontrollers) ? peripheral control interface : i 2 c bus master, spi master controller ? memory card controller : sd card/mmc, or memory stick tm (only in serial mode) ? power supply voltage : core section 2.5 v 0.15 v, i/o section 3.3 v 0.3 v ? standby current : 2 ma or less (target value when displaying partially on a small-sized lcd) ? package : 176-pin lqfp, 0.5 mm pitch, 24 mm (lqfp176-p-2424-0.50-bk)
pedl87v3116-02 oki semiconductor ML87V3116 2/47 block diagram external sdram data buffer (1 mbytes) data buffer controller rectangle copy controlle r display controller jpeg codec display output d16 host interface ycbcr /rgb 18/24 16 8/16-bit cpu bus video input interface camera/ video input ycbcr 8/16 i 2 c master camera control d64 16 spi peripheral control clock/power manager sd/mmc controller sd/mmc or memory stick memory stick controller
pedl87v3116-02 oki semiconductor ML87V3116 3/47 pin configuration (top view) 176-pin plastic lqfp 176 133 132 89 88 45 44 1 index mark (top side)
pedl87v3116-02 oki semiconductor ML87V3116 4/47 pin descriptions table-p1 pin list (1/7): video input related pin no. symbol i/o type description 139-144, 146, 147 vy7-0 i lvttl, pull-up video input data y/port 0 148-151, 153-156 vc7-0 i lvttl, pull-up video input data c/port 1 159 vhs i lvttl, pull-up video input horizontal synchronous signal 158 vvs i lvttl, pull-up video input vertical synchronous signal 161 vfid i lvttl, pull-up video input field id signal 160 vclk i lvttl, pull-down schmitt trigger video input clock table-p2 pin list (2/7): display output related pin no. symbol i/o type description 78, 77, 75-72 dg7-2 o 4ma drive display data g, bits 7-2 71 dg1ldp2 i/o input lvttl display data g, bit 1 or line drive pulse 2 70 dg0ldp3 i/o input lvttl display data g, bit 0 or line drive pulse 3 68-65, 63, 62 db7-2 o 4ma drive display data g, bits 7-2 61 db1ldp4 i/o input lvttl display data b, bit 1 or line drive pulse 4 60 db0hst2 i/o input lvttl display data b, bit 0 or horizontal start signal 2 87-82 dr7-2 o 4ma drive display data g, bits 7-2 80 dr1fdp2 i/o input lvttl display data r, bit 1 or line drive pulse 2 79 dr0fdp3 i/o input lvttl display data r, bit 0 or frame drive pulse 3 59 cp o 4ma drive data clock 57 ldp1 o 4ma drive line drive pulse 1 (hsync) 56 hst1 i/o input lvttl horizontal start signal 1 (gpio3) 55 fdp1 o 4ma drive frame drive pulse 1 (vsync) 54 fidf o 4ma drive current-alternating signal/field id signal 53 disp o 4ma drive display enable
pedl87v3116-02 oki semiconductor ML87V3116 5/47 table-p3 pin list (3/7): sdram interface related pin symbol i/o type description 137-134, 131-128, 118, 119, 121-126 mdq15-00 i/o input lvttl output 8ma drive memory data 104, 102-97, 95-90 ma12-00 o 8ma drive memory address 106,105 mba1-0 o 8ma drive memory bank address 109 mwen o 8ma drive write enable 111 mdqm o 8ma drive data mask 107 mrasn o 8ma drive row address strobe 108 mcasn o 8ma drive column address strobe 115-117 mcsn1-3 o 8ma drive memory chip select 112 mcke o 8ma drive memory clock enable 113 mclk o 8ma drive memory clock table-p4 pin list (4/7): host interface related pin symbol i/o type description 165-168, 170-173 d7-0 i/o input lvttl output 4ma drive host data bus 174, 175, 2-7, 9-12 ad11-00 i/o input lvttl output 4ma drive host address/data bus 13 csn i lvttl host access chip select 19 ren i lvttl host read enable 18 wen i lvttl host write enable 14 bsn i lvttl host bus strobe 17 dsn i lvttl host data strobe 20 bsyn o 4ma drive 3 states bus busy/wait 16 bclk i lvttl bus clock 21 int o 4ma drive interrupt 23-26 hmod3-0 i lvttl host bus mode select
pedl87v3116-02 oki semiconductor ML87V3116 6/47 table-p5 pin list (5/7): peripheral interface related pin symbol i/o type description 164 sda i/o input lvttl output 4ma drive open drain i 2 c bus serial data 163 scl o input lvttl output 4ma drive open drain i 2 c bus serial clock 50 ssdo o 4ma drive 3-state synchronous serial interface output data 49 ssdio i/o input lvttl output 4ma drive synchronous serial interface input/input-output data 48 ssck o 4ma drive synchronous serial interface clock 47 ssce o 4ma drive synchronous serial interface chip enable 29 sdcd3 i/o input lvttl output 4ma drive sd card interface data 3 30 sdcd2 i/o input lvttl output 4ma drive sd card interface data 2 31 sdcd1 i/o input lvttl output 4ma drive sd card interface data 1 32 sdmscd0 i/o input lvttl output 4ma drive sd card interface data 0 memory stick interface serial data 33 sdmscmd i/o input lvttl output 4ma drive sd card interface command memory stick interface bus state 34 sdmsclk o 4ma drive sd card interface clock memory stick interface serial clock 36 sdmsdtn i lvttl sd card interface insertion/extraction detection (active low) memory stick interface insertion/extraction detection 37 sdwp i lvttl sd card interface write protect 46 sdpwr o 4ma drive sd card interface power control table-p6 pin list (6/7): system control pin symbol i/o type description 42 refclk i lvttl reference clock 27 resetn i lvttl system reset 39-41 tmod2-0 i lvttl test mode (all fixed to "l") 51 tout o 4ma drive test output (open) 38 scan i lvttl test mode (fixed to "l")
pedl87v3116-02 oki semiconductor ML87V3116 7/47 table-p7 pin list (7/7): power supply pin symbol description 35, 52, 76, 88, 103, 127, 138, 176 vdd1 i/o power supply (3.3v) 28, 45, 69, 81, 110, 132, 133, 169 vss1 i/o ground 8, 22, 64, 89, 114, 152, 162 vdd2 core power supply (2.0v) 1, 15, 58, 96, 120, 145, 157 vss2 core ground 44 vddp pll power supply 43 vssp pll ground
pedl87v3116-02 oki semiconductor ML87V3116 8/47 functional description 1. general description the ML87V3116 is comprised of the following blocks. 1.1 video input interface the video input interface has two video input ports, and stores image data input from either port into the data buffer. 1.2 display interface the display interface outputs image data written into the data buffer to the external display unit. either color tft-lcd or tv format ca n be selected as an output format. 1.3 jpeg codec jpeg codec compresses image data using the jpeg method or decompresses a jpeg file into image data furthermore, jpeg codec can perform a motion-jpeg operation by repeating the above. jpeg codec manages the address of each frame using an index during a motion-jpeg operation. as the storage location of image data and jpeg files, bot h internal and external data buffers can be selected. 1.4 rectangle copy controller the rectangle copy controller copies the data in the speci fied rectangle area into another rectangle area within the data buffer. it can reduce the size or rotate images when copying them. 1.5 data buffer + data buffer controller this memory buffer stores video input data, display data and other image data. it is virtually handled as two-dimensional 16-bit deep memory. this memory supports images with more pixels than the memory capacity by varying the aspect ratio. furthermore, external memory can be added as an address extension of this memory. by storing multiple jpeg files into an extension data buffer during a motion-jpeg operation, for instance, the moving picture recoding/playback time can be extended. 1.6 host interface the host interface allows access to the control register of each block and two memory buffers, including external memory. a type of an interface that is compatible with various cpu buses can be selected by mode pin (hmod3-0) setting. 1.7 clock/power manager the clock/power manager controls the generation and stopping of the operating clocks of each block.
pedl87v3116-02 oki semiconductor ML87V3116 9/47 2. function of each block 2.1 video input interface 2.1.1 video input ports there are three types of video input formats. ? bt.656 format : an 8-bit format defined in itu-r rec. bt.656 ? 8-bit format : a format that deletes the synchronous reference code (eav/sav) from bt.656 format, and inputs the horizontal synchronous signal, vertical synchronous signal and field id separately ? 16-bit format : a format that inputs 8 bits of brightness y data, 8 bits of color difference c data into which cb/cr data are multiplexed, horizontal synchronous signal, vertical synchronous signal and field id either one of two inputs, y port (vy7-0) and c port (vc7-0), can be selected in bt.656 format. 8-bit format data uses only the y port. [control registers] ? vmdsel : input video format selection, 2 bits (write/read) ?00?: bt.656 format/ ?01?: 8-bit format/ ?10?: 16-bit format ? vptsel : port selection in bt.656 mode, 1 bit (write/read) 2.1.2 synchronous signal format for video input synchronous signals of video input include the horizontal synchronous signal (vhs), vertical synchronous signal (vvs), field id signal (fid) and data clock (vclk). a pulse polarity can be selected for each of the synchronous signals. the fid signal can be used only at the time of interl ace input. when the fid input does not operate, whether the input is an interlace input or a progressive input is automatically determined based on the pulse phase relationship between the vhs signal and the vvs signal. in the case of interlace input, an internal field id signal is generated. when vhs or vvs signal does not operate, it is determined as an itu-r rec. bt.656 input. then, an internal horizontal synchronous signal and vertical synchronous signal are generated from the synchronous reference code (eav/sav) included in the data. itu-r bt.656 format is based on the video data interface standard for tv format. however, if data is within the designated data range and uses the synchronous reference code (eav/sav), it can be input as a signal that conforms to the standard even if the image size is different. [control registers] ? hspol : horizontal synchronous signal polarity, 1 bit (write/read) ? vspol : vertical synchronous signal polarity, 1 bit (write/read) ? fidpol : field id polarity, 1 bit (write/read) ? hscyc : horizontal synchronous signal cycle, 12 bits (read only) ? vscyc : vertical synchronous signal cycle, 12 bits (read only) ? hvdet : vhs signal, vvs signal detection, 1 bit (read only) ? ipdet : interlace/progressive detection, 1 bit (read only)
pedl87v3116-02 oki semiconductor ML87V3116 10/47 2.1.3 input image format specify the image area to be loaded into the data buffer for video input. specify the start position and size of the effective image area for input synchronous signals using the control register. furthermore, specify the position on the data buffer where that image area is to be written using the address of the upper left origin. store the image area into the picture buffer using the data format of 16 bpp (bit per pixel) and ycbcr 4:2:2: (y 8 bits, cb/cr multiplexed 8 bits). in the case of interlace input, construct a single frame image with consecutive two fields. figure 2.1 input synchronization timing there are two capture modes in capture operation: 1-frame capture mode and continuous capture mode. in the 1-frame capture mode, one frame of data is written into the data buffer after starting a capture operation and then exits. in the continuous capture mode, after capturing one frame of image after starting a capture operation, the data of the next frame is captured from the successive vertical address again. the continuous capture mode can be ended by forced stop. images can be captured by thinning the number of input pixels and the number of frames. if images are captured by thinning the number of pixels, the size of an image to be captured gets smaller than the setting value according to that thinning rate. thinning the number of frames is effective when in the continuous capture mode, and the interval of frames to be captured can be specified. use the following frames rate as a guide in the continuous capture mode. ? up to 720 x 480 pixels: 30 frames/sec max. ? up to 1 million pixels: 15 frames/sec max. ? up to 2 million pixels: 10 frames/sec max. ? up to 4 million pixels: 3 frames/sec max. active video [hscyc] [viacth] [vistah] [vscyc] vvs vhs [vistav] [viactv]
pedl87v3116-02 oki semiconductor ML87V3116 11/47 [control registers] ? vitrig : starts image capture/status, 1 bit (write/read) at a write, starts image capture when ?1? is written, and stops forcibly when ?0? is written. at a read, ?1? indicates capturing, and ?0? indicates the completion of capture. ? vimod : image capture mode, 1 bit (write/read) ?0?: 1 frame capture ?1?: continuous frame capture ? vistah : horizontal effective image start position, 12 bits (write/read) ? vistav : vertical effective image start position, 12 bits (write/read) ? viacth : horizontal effective image size, 12 bits (write/read) ? viactv : vertical effective image size, 12 bits (write/read) ? videch : horizontal direction pixel thinning rate, 3 bits (write/read) ?000?: 1/1, ?001?: 1/2, ?010?: 1/4, ?011?: 1/8, ?100?: 1/16 ? videcv : vertical direction pixel thinning rate, 3 bits (write/read) ?000?: 1/1, ?001?: 1/2, ?010?: 1/4, ?011?: 1/8, ?100?: 1/16 ? vifitv : frame thinning rate, 4 bits (write/read) ?0000?: 1/1, ?0001?: 1/2, , ?1110?: 1/15, ?1111?: 1/16 ? vcapax : data buffer x address, 8-pixel unit 12 bits (write/read) ? vcapay : data buffer y address, 1- (or 8-) line unit 12 bits (write/read)
pedl87v3116-02 oki semiconductor ML87V3116 12/47 2.2 display interface 2.2.1 display output format the tft-lcd mode or tv mode can be selected as a display output format. ? tft-lcd mode : progressive scan, output synchronization, variable number of pixels ? tv mode : interlace scan, fixed to 525i or 625i [control registers] ? dofmt : display format, 1 bit (write/read) ?0?: tft-lcd mode ?1?: tv mode ? tvstd : tv format selection, 3 bits (write/read) ?000? : 525i, 27.0 mhz (ntsc equivalent, bt.656) ?001? : 525i, 13.5 mhz (ntsc equivalent, bt.601) ?010? : 525i, 12.272727 mhz (ntsc equivalent, square pixels) ?011? : 525i, 14.31818 mhz (ntsc equivalent, 4fsc) ?100? : 625i, 27.0 mhz (pal equivalent, bt.656) ?101? : 625i, 13.5 mhz (pal equivalent, bt.601) ?110? : 625i, 14.75 mhz (pal equivalent, square pixels) note: it is necessary to set the system clock to each frequency described above. 2.2.2 output synchronous signals the functions of the output synchronous signals partially vary with the display output format. function remarks sync. signal tft-lcd mode tv mode cp data clock data clock ldp1 line drive pulse 1 hsync (horizontal synchronous signal) ldp2 line drive pulse 2 (not used) ldp3 line drive pulse 3 (not used) ldp4 line drive pulse 4 (not used) hst1 horizontal start signal 1 (not used) pulse width: 1 cp hst2 horizontal start signal 2 (not used) pulse width: 1 cp fdp1 frame drive pulse 1 vsync (vertical synchronous signal) fdp2 frame drive pulse 2 (not used) possible to and with ldp4 fdp3 frame drive pulse 3 (not used) possible to or with ldp2 fidf current-alternating signal field id signal disp display enable display enable
pedl87v3116-02 oki semiconductor ML87V3116 13/47 ? cp : data clock the polarity of cp can be selected. ? ldp1-4 : line drive pulse (4 types) the pulse cycle is common to ldp1-4, and the pulse width, pulse phase and pulse polarity can be specified in units of the number of cp clocks. when in the tv mode, ldp1 is automatically set and used as a hsync. ? hst1, 2 : horizontal start signal (2 types) the pulse width is 1 cp clock, and the pulse cycle (common to two types), pulse phase and pulse polarity can be specified. ? fdp1-3 : frame drive pulse (3 types) the frame cycle (common to 3 types), pulse width, pulse phase and pulse polarity can be specified in units of the number of lines. by anding fdp2 with ldp4, a frame cycle pulse with a pulse width narrower than one line can be set. by oring fdp3 with fdp2, a drive pulse can be set twice in one frame. when in the tv mode, fdp1 is automatically set and used as a vsync. ? fidf : current-alternating drive signal, or field id signal a signal that inverts for each frame, or a signal that inverts for each number of specified lines. in the latter case, the logic at the beginning of a frame is inverted for each frame. when in the tv mode, fidf is automatically set so as to invert for each frame, and used as a field id signal. ? disp : display enable signal a signal that specifies display on/off set the pulse phases of the ?hst1, 2? and ?ldp1-4? signals using an internal, virtual horizontal synchronous signal as a reference. the ?fdp1-3? signals are synchronized with this virtual horizontal synchronous signal. set the pulse phases of the ?fdp1-3? signals using an internal, virtual vertical synchronous signal as a reference. set the horizontal and vertical effective periods of output data in the same manner. these settings can be changed in the tft-lcd mode. however, the values set are held even after switching to the tv mode; thus, display can be performed in the original state when returning to the tft-lcd mode again. the ?ldp2-4,? ?hst1, 2? and ?fdp2-3? signals can be used as gpios if they are not used as synchronous signals.
pedl87v3116-02 oki semiconductor ML87V3116 14/47 [control registers] ? cppol : synchronous polarity selection for cp and output data, 1 bit (write/read) ?0?: synchronizes on the rising edge of cp, ?1?: synchronizes on the falling edge of cp ? hlcyc : hst/ldp cycle (units of the number of cp clocks), 11 bits (write/read) ? hst1pol : hst1 pulse polarity selection, 1 bit (write/read) ?0?: positive pulse, ?1?: negative pulse (same for the following) ? hst1pos : hst1 pulse position, 11 bits (write/read) ? hst2pol : hst2 pulse polarity selection, 1 bits (write/read) ? hst2pos : hst2 pulse position, 11 bits (write/read) ? ldp1pol : ldp1 pulse polarity selection, 1 bits (write/read) ? ldp1st : ldp1 pulse's front edge position, 11 bits (write/read) ? ldp1ed : ldp1 pulse's rear edge position, 11 bits (write/read) ? ldp2pol : ldp2 pulse polarity selection, 1 bits (write/read) ? ldp2st : ldp2 pulse's front edge position, 11 bits (write/read) ? ldp2ed : ldp2 pulse's rear edge position, 11 bits (write/read) ? ldp3pol : ldp3 pulse polarity selection, 1 bits (write/read) ? ldp3st : ldp3 pulse's front edge position, 11 bits (write/read) ? ldp3ed : ldp3 pulse's rear edge position, 11 bits (write/read) ? ldp4pol : ldp4 pulse polarity selection, 1 bits (write/read) ? ldp4st : ldp4 pulse's front edge position, 11 bits (write/read) ? ldp4ed : ldp4 pulse's rear edge position, 11 bits (write/read) ? vfcyc : fdp cycle (units of the number of lines), 10 bits (write/read) ? fdp1pol : fdp1 pulse polarity selection, 1 bits (write/read) ? fdp1st : fdp1 pulse's front edge position, 10 bits (write/read) ? fdp1ed : fdp1 pulse's rear edge position, 10 bits (write/read) ? fdp2pol : fdp2 pulse polarity selection, 1 bits (write/read) ? fdp2st : fdp2 pulse's front edge position, 10 bits (write/read) ? fdp2ed : fdp2 pulse's rear edge position, 10 bits (write/read) ? fdp3pol : fdp3 pulse polarity selection, 1 bits (write/read) ? fdp3st : fdp3 pulse's front edge position, 10 bits (write/read) ? fdp3ed : fdp3 pulse's rear edge position, 10 bits (write/read) ? fdp2mix : positive pulse and synthesis between fdp2 and ldp4, 1 bit (write/read) ?0?: without synthesis, ?1?: with synthesis ? fdp3mix : positive pulse or synthesis between fdp3 and ldp2 bit (write/read) ?0?: without synthesis, ?1?: with synthesis ? acthst : horizontal start position of effective image data, 11 bits (write/read) ? acthed : horizontal end position of effective image data, 11 bits (write/read) ? actvst : vertical start position of effective image data, 10 bits (write/read) ? actved : vertical end position of effective image data, 10 bits (write/read)
pedl87v3116-02 oki semiconductor ML87V3116 15/47 ? ldp2io : specify the ldp2 signal in gpio6, 1 bit (write/read) "0": synchronous signal, "1": gpio (same for the following) ? ldp3io : specify the ldp3 signal in gpio5, 1 bit (write/read) ? ldp4io : specify the ldp4 signal in gpio4, 1 bit (write/read) ? hst1io : specify the hst1 signal in gpio3, 1 bit (write/read) ? hst2io : specify the hst2 signal in gpio2, 1 bit (write/read) ? fdp2io : specify the fdp2 signal in gpio1, 1 bit (write/read) ? fdp3io : specify the fdp3 signal in gpio0, 1 bit (write/read) ? gpin6-0 : gpio6-0 input/output mode, 7 bits (write/read) ? gpiod6-0 : gpio6-0 data, 7 bits (write/read) at a write, data is output to the gpio that corresponds to the bits of the output mode. at a read, the signal level of the gpio that corresponds to the bits of the input mode is read. reading the bits of the output mode and writing to the bits of the input mode are disabled. figure 2.2 output synchronization timing active image [hlcyc] [acthed] [acthst] [vfcyc] fdpn hstn [actvst] [actved] internal hs [hstnpos] ldpn [ldpnst] [ldpned] [fdpnst] [fdpned] internal vs
pedl87v3116-02 oki semiconductor ML87V3116 16/47 2.2.3 display data formats the rgb format or ycbcr format can be selected as a display data format. because the data in a data buffer is in 16-bit ycbcr, 4:2:2 format, color space conversion is performed after expanding into 24-bit, 4:4:4 format first. cb/cr data is interpolated when expanding from 4:2:2 format to 4:4:4 format. the color space conversion formula is in accordance with itu-r rec. bt-601. [control registers] ? dofmt : output data format, 2 bits (write/read) ?00?: rgb. 4:4:4, 24 bits ?01?: ycbcr 4:4:4, 24 bits ?10?: ycbcr 4:2:2, 16 bits (no conversion) ?11?: ycbcr 4:2:2, 8 bits, bt.656 ? dcintp : cb/cr interpolation method, 1 bit (write/read) ?0?: linear interpolation (average of preceding and succeeding data) ?1?: repeat of the previous data figure 2.3 display data formats dofmt=?00?: rgb, 4:4:4, 24 bits dg7-0 db7-0 dr7-0 g0 g1 g2 g3 g4 g5 g6 g7 b0 b1 b2 b3 b4 b5 b6 b7 r0 r1 r2 r3 r4 r5 r6 r7 dofmt=?01?: ycbcr, 4:4:4, 24 bits dg7-0 db7-0 dr7-0 y0 y1 y2 y3 y4 y5 y6 y7 cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 cr0 cr1 cr2 cr3 cr4 cr5 cr6 cr7 dofmt=?10?: ycbcr, 4:2:2, 16 bits dg7-0 db7-0 dr7-0 y0 y1 y2 y3 y4 y5 y6 y7 cb0 cr0 cb2 cr2 cb4 cr4 cb6 cr6 (don?t care)
pedl87v3116-02 oki semiconductor ML87V3116 17/47 2.2.4 display data area partition, display/hide the effective data area of the display output can be divided into four partitions. horizontal division or vertical division can be selected, and the data buffer address of data to be displayed in each of the four areas can be specified individually. also, the specified area can be hidden. hidden ar eas are not used to read the data buffers. [control registers] ? dasmod : display area partition mode, 1 bit (write/read) ?0?: horizontal partition, ?1?: vertical partition ? divap1 : display area 0-1 partition point, 10 bits (write/read) ? divap2 : display area 1-2 partition point, 10 bits (write/read) ? divap3 : display area 2-3 partition point, 10 bits (write/read) ? da0sax : data buffer read start x address for display area 0, 8-pixel units 12 bits (write/read) ? da0say : data buffer read start y address for display area 0, 8-line units 12 bits (write/read) ? da1sax : data buffer read start x address for display area 1, 8-pixel units 12 bits (write/read) ? da1say : data buffer read start y address for display area 1, 8-line units 12 bits (write/read) ? da2sax : data buffer read start x address for display area 2, 8-pixel units 12 bits (write/read) ? da2say : data buffer read start y address for display area 2, 8-line units 12 bits (write/read) ? da3sax : data buffer read start x address for display area 3, 8-pixel units 12 bits (write/read) ? da3say : data buffer read start y address for display area 3, 8-line units 12 bits (write/read) ? dpenb0-3 : partition area display enable, 4 bits (write/read) ?0?: display, ?1?: hide (each bit) ? blkcol : output data in hidden area, 1 bit (write/read) ?0?: all ?l?, ?1?: all ?h? ? dopsng : positive/negative mode of output data, 4 bits (write/read) ?0?: normal mode (positive), ?1?: all bits reversed (negative) ? disp : disp signal output level, 1 bit (write/read) ?0?: ?l? level, ?1?: ?h? level
pedl87v3116-02 oki semiconductor ML87V3116 18/47 horizontal partition mode vertical partition mode figure 2.4 display area partitioning [acthed] - [acthst] area 0 [actved] - [actvst] area 1 area 2 area 3 [divap1] [divap2] [divap3] display screen [acthed] - [acthst] area 0 [actved] - [actvst] area 1 area 2 area 3 [divap1] [divap2] [divap3] display screen
pedl87v3116-02 oki semiconductor ML87V3116 19/47 figure 2.5 display address specification (example in vertical partition mode) area 0 area 1 area 2 area 3 display outputs [da1sax] [da1say] data buffer [da3sax] [da3say] [da0sax] [da0say] [da2sax] [da2say]
pedl87v3116-02 oki semiconductor ML87V3116 20/47 2.3 jpeg codec 2.3.1 general description jpeg codec compresses and decompresses image data. when compressing images, jpeg codec uses a rectangle ar ea specified in the data buffer as the source image, sequentially reads data into block forms, compresses data using the jpeg method, and then converts the compressed data to a compressed data file in the jfif format. this compressed data file is written in the rectangle area from the start address specified in the data buffer. compression formats such as block interleave are in accordance with the jpeg baseline standard. set the source image size, quantization table and huffman table using control registers in advance. color components only support the 2:1:1 format equivalent to 4:2:2 of video. for image compression, the sequential compression of input image data can be performed by conducting an operation simultaneously with image input. when decompressing images, jpeg codec sequentially reads a compressed data file from the start address specified in the data buffer, decompresses data using th e jpeg method, placing restored data block again, and reconstructing images. decompressed images are sequen tially written from the start address specified in the data buffer in block units. the image size, quantization table and huffman table are extracted from a compressed data file in the jfif format. 2.3.2 still picture mode and moving picture mode compression and decompression operations are available in two modes: still picture mode and moving picture mode. in the still picture mode, an operation starts by writing to the startup register, and ends when the processing of one image ?frame? completes. also, an operation can temporarily be stopped for each number of specified lines. this makes it possible to process images having the number of pixels larger than the memory buffer capacity. it does not relate to the restart marker rstm. the moving picture mode is a repetition of operations in the still picture mode. by automatically managing the addresses of compressed data files, multiple files can sequentially be compressed or decompressed. an operation in the moving picture mode is started by writing to the startup register, and ended after the completion of a series of specified operatio ns, or the same operation is repeated. when recording (compressing) moving pictures, the operation is synchronized with the frame timing of video input. when playing back (decompressing) moving pictures, the operation is synchronized with the frame timing of video output. during an moving picture recording operation, the same image size, quantization table and huffman table are used for all frames. they cannot be changed during recording.
pedl87v3116-02 oki semiconductor ML87V3116 21/47 2.3.3 moving picture mode the size of a compressed data file in each frame is restricted by the segment size specification. for the segment size, any of 256/512/1k/2k/4k/8k/16k /32k/64k bytes can be selected according to the image size. (be careful so that the compressed data file size does not exceed the segment size.) the addresses of compressed data files are managed using index pointers. an index pointer is 16 bits in size, and indicates the number of a frame to be compressed or decompressed. a frame number is equivalent to the upper bit of the start address of a compressed data file. an actual address is a value that is shifted to the left by the number of bits for the segment size. an index pointer is a sort of a counter. when recording moving pictures, the value of an index poi nter is incremented from 0 to the specified number of frames for each input frame. when playing back moving pictures, various playback operations can be performed, such as ?normal play? that increments an index pointer for each display frame, ?reverse play? that decrements an index pointer, ?slow play? that increments an index pointer for 2/4/8/15/30/60 display frames, and "fast forward play" that skips an index pointer at intervals of specified numbers. one or two locations can be specified as the source image read addresses when compressing and playback image write addresses when decompressing. if two lo cations are specified at the same time, they can alternately be switched for each frame. when playing back moving pictures, a double-buffer operation can be performed, achieving smooth moving picture display.
pedl87v3116-02 oki semiconductor ML87V3116 22/47 2.4 rectangle copy controller 2.4.1 general description the rectangle copy controller reads data from the specifi ed rectangle area (copy source), reduces and/or rotates it, and writes it into another specified area (copy destination). specify the start addresses (x start, y start) (upper left coordinates) of the copy source and copy destination and the rectangle size (x size, y size), and perform a copy operation using a startup command. when copying, either reduction or rotation can be specified. for the reduction magnification, x1 (no reduction), x1/2, x1/8, x1/16, or x1/32 can be selected. for rotation, 0 deg. (no rotation), 90 deg., 180 deg. or 270 deg. (all clockwise rotations) can be selected. the rectangle size of the copy destination is set as the size calculated from the rectangle size of the copy source according to the reduc tion/rotation function. reduction and rotation cannot be specified at the same time. also, data buffer access from the host cpu goes through this rectangle copy controller. when writing from the host, specify the host as the copy source, and also specify the start address of the copy destination and the rectangle size. when continuous writes are performed from the host, data is sequentially written into the specified rectangle area. when reading from the host, specify the host as the copy destination, and also specify the start address of the copy source and the rectangle size. when continuous reads are performed from the host, data is sequentially read from the specified rectangle area. table 2.4.1 copy function list no. function name functional description note 1 rotate rotate data in a rectangle area in the data buffer , and copy it into an area of the copy destination. <> clockwise rotation: 0 , 90 , 180 , 270 2 reduce reduce data in a rectangle area in the data buffer in both the horizontal and vertical directions, and copy it into an area of the copy destination. <> horizontal: x1/2, x1/4, x1/8, x1/16, x1/32 vertical: x1/2, x1/4, x1/8, x1/16, x1/32 3 fill fill a rectangle area in the data buffer with the color data (y, cb, cr) specified from the host cpu. 4 host access read data in a rectangle area in the data buffer by the host cpu. also, write data sent from the host cpu into a rectangle area in the data buffer .
pedl87v3116-02 oki semiconductor ML87V3116 23/47 2.4.2 specifying a rectangle area specify a rectangle area using the start address (xadrs, yadrs) and size (xsize, ysize). for the start address, specify the start addresses using an upper left point of a rectangle area even when copying by rotating. be sure to specify a rectangle area within the range of the buffer memory size in use. horizontal x vertical y buffer memory area copy source (xfrom_adrs, yfrom_adrs) xsize ysize copy source copy destination copy destination (xto_adrs, yto_adrs) copy destination for copy (rotation) copy figure 2.4.2 image of rectangle area specification
pedl87v3116-02 oki semiconductor ML87V3116 24/47 2.4.3 rotation processing in block the copy controller rotates the rectangle area specified by the host cpu, and copies it into an area of the copy destination. c data when rotating 90 or 270 is thinned out and its position is adjusted. <> clockwise rotation: 0 , 90 , 180 , 270 <> rectangle area start address of copy source (xfrom_adrs, yfrom_adrs) rectangle area size of copy source (xsize, ysize) rotation angle (angle) start address of copy destination (xto_adrs, yto_adrs) <> minimum pixel unit for rotation processing: 16 pixels x 16 lines rectangle area start address unit of copy source: horizontal direction: 16 pixels vertical direction: 4 lines rectangle area start address unit of copy destination: horizontal direction: 16 pixels vertical direction: 4 lines buffer memory area copy source(xfrom_adrs) xsize ysize copy destination (specified coordinates) (xto_adrs, yto_adrs) copy source 16 16 pixels 90 rotation 180 rotation 270 rotation 0 rotation c d e f g h i j c d e f g h i j c d e f g h i j c d e f g h i j g h i j c d e f (yfrom_adrs) figure 2.4.3 example of copy destin ation coordinate specification and processing sequence for copy by rotating
pedl87v3116-02 oki semiconductor ML87V3116 25/47 2.5 data buffer and controller 2.5.1 general description a data buffer is a memory buffer having two-dimensional addresses. the memory size is 1 mbyte and the depth is 1 pixel (16 bits). write/read access to the data buffer is always performed via block access. external sdram is called an extension data buffer, which is assumed as an address extension area of the internal data buffer. however, there are restrictions on access to extension data buffers. if the internal data buffer is used two-dimensionally, the x size (horizontal direction) and y size (vertical direction) of the memory size can be changed. ? data buffer size variations (x size y size) 4096 128 pixels 2048 256 pixels 1024 512 pixels 512 1024 pixels the following types of sources are available for access to data buffers: a) video input write b) display output read c) jpeg block access read/write d) jpeg compressed data file read/write e) copy source read f) copy destination write g) host access read/write h) refresh for access to the internal data buffer, up to four acce ss sources can simultaneously (time sharing) be used among the access sources listed above. however, jpeg accesses of c) and d) are always carried out simultaneously in pair. also, during the operations of the copy functions e) and f), the host access g) cannot be carried out simultaneously. for access to an extension data buffer, always only one access source can be used.
pedl87v3116-02 oki semiconductor ML87V3116 26/47 horizontal (4095 pixels max.) v ertical (1024 lines max.) internal sdram external sdram vertical (24703 lines max.) vertical (4940 lines max.) vertical (98815 lines max.) vertical (197631 lines max.) horizontal (2047 pixels max.) horizontal (511 pixels max.) vertical horizontal (1023 pixels max.) (0,0) figure 2.5.1 image of buffer memory size
pedl87v3116-02 oki semiconductor ML87V3116 27/47 logical address 181ffff 0020000 001ffff 0000000 maximum (when configured with 512 mbits x 3) extension data buffer 3 extension data buffer 2 extension data buffer 1 internal data buffer (8 mbits) figure 2.5.2 data buffer memory map y(max) x(min) = 128 y(min) x(max) = 1024 example of xsize = 512 x y invalid 00000000 internal data buffer row col (8192x16x64b) example extension data buffer bank row col (4x8192x512x16b) -1 make the least significant 2 bits of y and x as the least significant 4 bits of an one-dimensional address. 25 bits inv alid figure 2.5.3 address conversion
pedl87v3116-02 oki semiconductor ML87V3116 28/47 2.6 host interface 2.6.1 general description the host interface allows access to the control register of each block and the internal/external data buffers. a type of an interface that is compatible with variou s cpu buses can be selected by mode pin (hmod3-0) setting. also, there are an i 2 c bus master and synchronous serial interface master that can directly be controlled by the host interface. table-f5.1 host interface bus modes hmod [3:0] bus type address/ data bus bus control reference cpu *1) 0 0 0 0 a0 csn, wen, ren, busy renesas sh-1, sh-2, h8s fujitsu f 2 mc-16f, fr30 toshiba tlcs-900/h2 0 0 0 1 a1 as, wen, ren, busy renesas sh-4, sh-3 *2) 0 0 1 0 a2 bsn, wen, ren, ack motorola mcf5204 toshiba tx39 0 0 1 1 ? (reserved) ? 0 1 0 0 a4 bsn, rwn, dsn, ack toshiba tx19 motorola mcf5206 mpc801/850, m68k 0 1 0 1 a5 bsn, rwn, dsn, busy renesas m32r, nec v830 intel sa-110 0 1 1 x ? separate a[18:00] d[07:00] (reserved) ? 1 0 0 0 b0 asn, wen, ren, busy renesas sh-1, sh-2 nec v850, 78k/iv renesas m16c oki msm66k, 80c51 1 0 0 1 b1 as, wen, ren, busy fujitsu f 2 mc-16l toshiba tlcs-900 renesas m16c oki msm66k, 80c51 1 0 1 x ? 1 1 x x ? multiplex a[18:16] ad[15:00] (reserved) ? *1) the cpus listed above are reference models. upon verifying the specification of the cpu bus you are using, select a setting mode. *2) in the case of the sh-3, invert the bus strobe signal and input to the bsn pin.
pedl87v3116-02 oki semiconductor ML87V3116 29/47 2.6.2 bus control signals the assignment of the bus control signals to the input/output pins is determined by the host interface bus mode. table-f5.5.1 bus control signals bus type pin name a0 a1 a2 a4 a5 b0 b1 a18-16 a18-16 a18-16 a18-16 a18-16 a18-16 a18-16 a18-16 ad15-00 a15-00 a15-00 a15-00 a15-00 a15-00 ad15-00 ad15-00 d07-00 d07-00 d07-00 d07-00 d07-00 d07-00 ? ? regs regs regs regs regs regs regs regs csn csn csn csn csn csn csn csn ren ren ren ren rwn rwn ren ren wen wen wen wen ? ? weln weln bsn ? bs bsn bsn bsn asn as dsn ? ? ? ? ? wehn wehn bsyn bsyn bsyn ack ack bsyn bsyn bsyn bclk bclk bclk bclk bclk bclk bclk bclk regs : memory/register address space selection: ?l?: memory, ?h?: register csn : chip select (active ?l?) ren : read enable (active ?l?) wen : write enable (active ?l?) wehn : upper byte write enable (active ?l?) weln : lower byte write enable (active ?l?) rwn : read/write selection: ?l?: write, ?h?: read bsn : bus start (active ?l?) asn : address strobe (active ?l?) dsn : data strobe (active ?l?) bsyn : bus busy or wait, variable widt h according to wait time (active ?l?) ack : data acknowledge, 1 clock width (active ?l?) bclk : bus clock
pedl87v3116-02 oki semiconductor ML87V3116 30/47 [bus interface timing] (1) a0-type write (2) a0-type read mem bclk csn a18-00 reg regs wen d7-0 bsyn (write) (z) ren (read) (z) mem bclk csn a18-00 reg regs d7-0 bsyn
pedl87v3116-02 oki semiconductor ML87V3116 31/47 (3) a1-type write (4) a1-type read mem bclk csn a18-00 reg regs wen d7-0 bsyn (write) (z) bs ren (read) (z) mem bclk csn a18-00 reg regs d7-0 bsyn bs
pedl87v3116-02 oki semiconductor ML87V3116 32/47 (5) a2-type write (6) a2-type read mem bclk csn a18-00 reg regs wen d7-0 ack (write) (z) bsn mem bclk csn a18-00 reg regs ren d7-0 ack (read) (z) bsn
pedl87v3116-02 oki semiconductor ML87V3116 33/47 (7) a4-type write (8) a4-type read mem bclk csn a18-00 reg regs rwn d7-0 ack (write) (z) bsn mem bclk csn a18-00 reg regs d7-0 ack (read) (z) bsn rwn
pedl87v3116-02 oki semiconductor ML87V3116 34/47 (9) a5-type write (10) a5-type read mem bclk csn a18-00 reg regs d7-0 bsyn (write) (z) bsn rwn mem bclk csn a18-00 reg regs d7-0 bsyn (read) (z) bsn rwn
pedl87v3116-02 oki semiconductor ML87V3116 35/47 (11) b0-type write (12) b0-type read bclk csn a18-16 regs ad15-0 d (write) bsyn (z) asn a d (write) a wehn weln bclk csn a18-16 regs ad15-0 bsyn (z) asn a a ren d (read) d (read)
pedl87v3116-02 oki semiconductor ML87V3116 36/47 (13) b1-type write (14) b1-type read mem bclk csn a18-16 regs ad15-0 d (write) bsyn (z) as a wehn weln d (write) a mem bclk csn a18-16 regs ad15-0 bsyn (z) as a a d (read) ren d (read)
pedl87v3116-02 oki semiconductor ML87V3116 37/47 2.7 clock/power manager 2.7.1 general description the system clock of the ML87V3116 uses the same pixel clock frequency as display output or a frequency of x2, x4 or x8. this clock generates the refclk input by a built-in pll using simple integer ratio n/m (n and m are 1 to 255) as a reference. power saving can be achieved by setting to a slower system clock frequency at standby. the video input clock vclk and host interface bus clock bclk are asynchronous with the system clock. the frequency ratio to the system clock can be set in a range of 1:10 to 10:1. the system clock is distributed to each function bl ock and its on/off can be controlled individually. the types of a clock to be distributed are: ? video input interface ? display output interface ? jpeg codec ? rectangle copy controller ? data buffer controller and internal sdram ? external sdram clock for extension data buffers ? i 2 c bus master ? synchronous serial interface (spi) master ? sd card controller ? memory stick controller
pedl87v3116-02 oki semiconductor ML87V3116 38/47 2.7.2 clock generation the system clock of the ML87V3116 uses x2, x4 or x8 of the pixel clock frequency of display output. this clock generates the refclk input by a built-in pll using simple integer ratio n/m (n and m are 1 to 255) as a reference. (system clock = n/m ? refclk) the clock for jpeg is generated by the frequency divider of another system, and can be operated even at a slower speed than the system clock. the system clock is distributed to internal modules. the clock for each module can control a clock enable individually by register control, so that it can be used for the purpose of reducing power consumption. figure 2.7.1 clock generation built-in pll 1/m system clock 1/n refclk 1/l : re g iste r mdiv ndiv ldiv 1/j j div jpeg clock 1/2 display output pixel clock
pedl87v3116-02 oki semiconductor ML87V3116 39/47 absolute maximum ratings parameter symbol condition rating unit i/o power supply vdd1 ta = 25 c ?0.3 to +4.6 v core power supply vdd2 ta = 25 c ?0.3 to +3.6 v pll power supply vddp ta = 25 c ?0.3 to +3.6 v input voltage vi ta = 25 c ?0.3 to vdd1+0.3 v output voltage vo ta = 25 c ?0.3 to vdd1+0.3 v output short-circuit current ios ? 50 ma power dissipation pd ta = 25 c 1.0 w storage temperature tstg ? ?65 to +150 c recommended operating conditions parameter symbol condition range unit i/o power supply vdd1 vss1 = vss2 = 0 v 3.0 to 3.6 v core power supply vdd2 vss1 = vss2 = 0 v 2.35 to 2.65 v pll power supply vddp vssp = 0 v 2.35 to 2.65 v operating temperature top ? 0 to 70 c note: turn on the power in the order of vdd1, vdd2, and then vddp. to shut down the power, use the reverse order. pin capacitance (vdd1= 3.3v 0.3v, vdd2=vddp= 2.5v 0.15v, vss= 0v, f = 1 mhz, ta = 25c) parameter symbol min. max. unit input capacitance c i - 7 pf input/output capacitance c io1 - 7 pf output capacitance c o - 7 pf
pedl87v3116-02 oki semiconductor ML87V3116 40/47 electrical characteristics dc characteristics (vdd1 = 3.3 v 0.3 v, vdd2 = vddp = 2.0 v 0.15 v, vss = 0 v, ta = 0 to 70 c) parameter symbol condition min. typ. max. unit ?h? level input voltage vih1 ? 2.0 - vdd1+0.3 v ?l? level input voltage vil1 ? vss-0.3 - 0.8 v ?h? level output voltage voh1 ioh = 8ma 0.8 vdd1 ? ? v ?l? level output voltage for sdram vol1 iol = 8ma ? ? 0.2 vdd1 v ?h? level output voltage voh2 ioh = 4ma 0.8 vdd1 ? ? v ?l? level output voltage others vol2 iol = 4ma ? ? 0.2 vdd1 v input leakage current ili ? ? 10 ? +10 a output leakage current ilo ? ? 10 ? +10 a ?h? level output current (pull-down) iih vi=vdd1 20 - 200 a ?l? level output current (pull-up) iil vi=0v -200 - -20 a dynamic idd1 ? ? 200 ma when in the nondisplay state idd2 fope = 54mhz outputs open ? ? 10 ma power supply current (internal core) *1 standby idds vi=0v ? ? 5 ma *1 power supply current mentioned here does not include the supply current for the i/o buffer.
pedl87v3116-02 oki semiconductor ML87V3116 41/47 ac characteristics (vdd1 = 3.3 v 0.3 v, vdd2 = vddp = 2.0 v 0.15 v, vss = 0 v, ta = 0 to 70 c) parameter symbol condition min. max. unit operating frequency (internal clock) fope ? ? 56.0 mhz bclk clock period tck1 ? 30 ? ns bclk ?h? level pulse width twh1 ? 12 ? ns bclk ?l? level pulse width twl1 ? 12 ? ns input setup time ( bclk) ts1 ? 5 ? ns input hold time ( bclk) th1 ? 5 ? ns output delay time (bclk ) *1 tpd1 cl = 15pf 5 15 ns refclk clock period tck2 ? 36 ? ns refclk ?h? level pulse width twh2 ? 14 ? ns refclk ?l? level pulse width twl2 ? 14 ? ns output hold time (cp ) cp period = tck2 thcp cl = 15pf tck2 = tck2(max) 0 10 ns *1 values for the output signal timing characteristics have been measured at the vdd1/vdd2 points. *2 activate the clock signal to be input to the refclk pin by the time the specified voltage is reached after power is turned on.
pedl87v3116-02 oki semiconductor ML87V3116 42/47 timing diagrams (1) ac characteristics twh1 twl1 tck1 bcl k input (csn, bsn, dsn, wen, ren, ad, d) ts1 th1 th1 ts1 output (bsyn, int, ad, d) tpd1 tpd1 vih vil vih vil vih vil vdd/2 vdd/2 (a) host interface (b) lcd interface twh2 twl2 tck2 refcl k output (drn, dgn, dbn, lcp, frp, df) thcp vih vil cp vdd/2 vdd/2 fig. a-1 ac characteristics twh3 twl3 tck3 vcl k input (vhs, vvs, vfid, vyn, vcn) ts1 th1 vih vil vih vil (c) video interface
pedl87v3116-02 oki semiconductor ML87V3116 43/47 (2) color tft, horizontal timing dr7-0 cp ldp dg7-0 db7-0 0 1 2 3 4 5 6 7 8 n-2 n-1 (acthed-acthst) [tcp] (hlcyc+1) [tcp] tcp n-2 n-1 0 1 2 3 4 5 6 7 8 n-2 n-1 n-2 n-1 0 1 2 3 4 5 6 7 8 n-2 n-1 n-2 n-1 (3) color tft, vertical timing dr7-0 dg7-0 db7-0 ldpn (actved-actvst) [tlcp] (vfcyc+1) [tlcp] tlcp fdpn line 0 line 1 line 2 line 3 line 0 line 1 line 2 line 3 line 0 line 1 line 2 line 3 (fdpned-fdpnst)
pedl87v3116-02 oki semiconductor ML87V3116 44/47 package dimensions lqfp176-p-2424-0.50-bk mirror finish package material epoxy resin lead frame material 42 alloy pin treatment solder plating ( 5m) package weight (g) 1.87 typ. 5 rev. no./last revised 3/nov. 28, 1996 notes for mounting the surface mount type package the surface mount type packages are very susceptible to he at in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact oki?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). ( unit: mm )
pedl87v3116-02 oki semiconductor ML87V3116 45/47 revision history page document no. date previous edition current edition description pedl87v3116-01 jan. 30, 2004 ? ? preliminary edition 1 pedl87v3116-02 sep. 21, 2004 ? ?
pedl87v3116-02 oki semiconductor ML87V3116 46/47 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. wh en planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third party?s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party?s right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communicatio n equipment, measurement equipment, consumer electronics, etc.). these products are not, unless specifi cally authorized by oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, tra ffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 2004 oki electric industry co., ltd.

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